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19-1116; Rev 1; 11/96
Microprocessor-Compatible, 14-Bit DACs
_______________General Description
The MX7534/MX7535 are high-performance, CMOS, monolithic, 14-bit digital-to-analog converters (DACs). Wafer-level, laser-trimmed, thin-film resistors and temperature-compensated NMOS switches assure operation over the full operating temperature range with exceptional linear and gain stability. The MX7534 accepts right-justified data in two bytes from an 8-bit bus, while the MX7535 operates with a 14-bit data bus with separate MS-byte and LS-byte select controls. In addition, all digital inputs are compatible with both TTL and 5V CMOS-logic levels. The MX7534/MX7535 are intended for unipolar operation, but may be operated as bipolar DACs with additional external components. Both devices are protected against CMOS latchup, and neither requires the use of external Schottky protection diodes. The MX7534 is available in 20-pin narrow (0.3") DIP, wide SO, or PLCC packages. The MX7535 is available in 28-pin, 600 mil wide DIP, wide SO, or PLCC packages.
____________________________Features
o 14-Bit Monotonic Over Full Temperature Range o Full 4-Quadrant Multiplication o P-Compatible, Double-Buffered Inputs o Exceptionally Low Gain Tempco (2.5ppm/C) o Low Output Leakage (<20nA) Over Temp. o Low Power Consumption o TTL and CMOS Compatible
MX7534/MX7535
______________Ordering Information
PART
MX7534KN MX7534JN MX7534KCWP MX7534JCWP MX7534KP MX7534JP MX7534J/D MX7534BQ MX7534AQ MX7534BD MX7534AD MX7534KEWP MX7534JEWP MX7534TQ MX7534SQ MX7534TD MX7534SD
TEMP. RANGE
0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C
PIN-PACKAGE INL (LSBs)
20 Plastic DIP 20 Plastic DIP 20 SO 20 SO 20 PLCC 20 PLCC Dice* 20 CERDIP 20 CERDIP 20 Ceramic SB 20 Ceramic SB 20 SO 20 SO 20 CERDIP 20 CERDIP 20 Ceramic SB 20 Ceramic SB 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2
________________________Applications
Machine and Motion Control Systems Automatic Test Equipment Digital Audio P-Controlled Calibration Circuitry Programmable-Gain Amplifiers Digitally Controlled Filters Programmable Power Supplies
Ordering Information continued at end of data sheet. *Dice are tested at +25C, DC parameters only.
_________________Pin Configurations
TOP VIEW
REF 1 RFB 2 IOUT 3 AGNDS 4 AGNDF 5 DGND 6 D7 7 D6 8 20 VSS 19 VDD 18 CS 17 WR
_______________Functional Diagrams
VDD 19 REF 1 14-BIT DAC 14 DAC REGISTER 6 MS INPUT REGISTER 8 LS INPUT REGISTER
MX7534
2 RFB 3 IOUT 4 AGNDS 5 AGNOF 15 A1 16 A0 18 CS 17 WR
MX7534
16 A0 15 A1 14 D0 13 D1 12 D2 11 D3
CONTROL LOGIC
D5 9 D4 10
DIP/SO/PLCC/Ceramic SB
MX7535 at end of data sheet.
7-14 D7-D0
6 DGND
20 VSS
Functional diagrams continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ............................................................-0.3V, +17V VSS to AGND .............................................................-15V, +0.3V REF to AGND (MX7534) ......................................................25V REFS to AGND (MX7535) ....................................................25V REFF to AGND (MX7535) ....................................................25V RFB to AGND.......................................................................25V Digital Input Voltage to DGND.........................-0.3V, VDD + 0.3V IOUT to DGND .................................................-0.3V, VDD + 0.3V AGND to DGND ...............................................-0.3V, VDD + 0.3V Continuous Power Dissipation (TA = +70C) 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 28-Pin Plastic DIP (derate 14.29mW/C above +70C) ......1.14W 20-Pin SO (derate 10.00mW/C above +70C)..............800mW 28-Pin SO (derate 12.50mW/C above +70C).....................1W 20-Pin PLCC (derate 10.00mW/C above +70C) .........800mW 28-Pin PLCC (derate 10.53mW/C above +70C) .........842mW 20-Pin CERDIP (derate 11.11mW/C above +70C)......889mW 28-Pin CERDIP (derate 16.67mW/C above +70C)........1.33W 20-Pin Ceramic SB (derate 11.76mW/C above +70C) .............................941mW 28-Pin Ceramic SB (derate 20.00mW/C above +70C) ................................1.6W Operating Temperature Ranges MX753_J/K ............................................................0C to +70C MX753_A/B ........................................................-25C to +85C MX753_EW_.......................................................-40C to +85C MX753_S/T.......................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +11.4V to +15.75V (Note 1), VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error Gain Temperature Coefficient (Note 2) INL MX753_K/B/T MX753_J/A/S Guaranteed Monotonic Measured with internal RFB, MX753_K/B/T includes effects of leakage MX753_J/A/S current and gain TC MX753_K/B/T MX753_J/A/S All digital inputs at 0V Output Leakage Current IOUT All digital inputs at 0V, VSS = 0V TA = +25C TA = TMIN to TMAX MX753_J/K/A/B MX753_S/T 0.5 0.5 14 1 2 1 4 LSB 8 2.5 5 5 25 150 nA ppm/C Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUT Reference Voltage Input Resistance (Note 3) DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance (Note 2) CIN VINH VINL Digital inputs at 0V or VDD TA = +25C TA = TMIN to TMAX 2.4 0.8 1 10 7 V V A pF RREF 3.5 6 10 k
2
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Microprocessor-Compatible, 14-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +11.4V to +15.75V (Note 1), VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER REQUIREMENTS Positive Supply-Voltage Range Negative Supply-Voltage Range Positive Supply Current Negative Supply Current VDD VSS IDD ISS For specific performance For specific performance Digital inputs at VINH or VINL Digital inputs at 0V or VDD MX7534 MX7535 11.4 -200 15.75 -500 3 4 500 V mV mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
MX7534/MX7535
Note 1: Specifications are guaranteed for VDD of +11.4V to +15.75V. At VDD = +5V, device is still functional with degraded specifications. Note 2: Guaranteed by design, not tested. Note 3: Resistors have a typical -300ppm/C tempco.
AC PERFORMANCE CHARACTERISTICS (Note 4)
(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGND (VAGNDS for MX7535) = VSS = 0V, output amplifier is AD544*, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Output Current Setting Time SYMBOL CONDITIONS TA = +25C, to 0.003% of full-scale range, IOUT load = 100 II 13pF, DAC register alternately loaded with all 1s and all 0s Measured with VREF = 0V, IOUT loads = 100 II 13pF, DAC register alternately loaded with all 1s and all 0s VREF = 10V, 10kHz sine wave, DAC register loaded with all 0s VDD = 5% COUT TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX MIN TYP 0.8 MAX 1.5 UNITS s
Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error (Note 5) Power-Supply Rejection Output Capacitance (IOUT Pin) Output Noise Voltage Density (10Hz-100kHz)
50 3
nV-sec
mVp-p 5 0.01 0.02 260 130 15 %/% pF nV/Hz
DAC register loaded with all 1s DAC register loaded with all 0s Measured between RFB and IOUT
Note 4: These characteristics are included for design guidance only, and are not subject to test. Note 5: Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
* AD544 is an Analog Devices part.
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
TIMING CHARACTERISTICS (MX7534)
(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGND = VSS = 0V, TA = TMIN to TMAX, unless otherwise noted. See Figure 1a for timing diagram.) PARAMETER Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time SYMBOL t1 t2 TA = +25C t3 TA = -25C to +85C TA = -55C to +125C TA = +25C Data Hold Time Chip-Select to Write-Setup Time Chip-Select to Write-Hold Time Write Pulse Width t4 t5 t6 TA = +25C t7 TA = -25C to +85C TA = -55C to +125C TA = -25C to +85C TA = -55C to +125C CONDITIONS MIN 0 0 60 70 80 20 20 30 0 0 170 200 240 ns ns ns ns ns TYP MAX UNITS ns ns
TIMING CHARACTERISTICS (MX7535)
(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA = TMIN to TMAX, unless otherwise noted. See Figure 1b for timing diagram.) PARAMETER CSMSB or CSLSB to WR Setup Time CSMSB or CSLSB to WR Hold Time LDAC Pulse Width SYMBOL t1 t2 TA = +25C t3 TA = -25C to +85C TA = -55C to +125C TA = +25C Write Pulse Width t4 TA = -25C to +85C TA = -55C to +125C TA = +25C Data-Setup Time t5 TA = -25C to +85C TA = -55C to +125C TA = +25C Data-Hold Time t6 TA = -25C to +85C TA = -55C to +125C CONDITIONS MIN 0 0 170 200 240 170 200 240 140 160 180 20 20 30 ns ns ns ns TYP MAX UNITS ns ns
4
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Microprocessor-Compatible, 14-Bit DACs
__________Pin Description (MX7534)
PIN NAME REF RFB IOUT AGNDS FUNCTION Reference Input to DAC Feedback Resistor. Used to close the loop around an external op amp. Current Output Analog Ground Sense. Reference point for external circuitry. AGNDS should carry minimum current. Analog Ground Force. Carries current from internal analog ground connections. AGNDS and AGNDF are tied together internally. Digital Ground Data Bit 7 Data Bit 6 Data Bit 5 or Data Bit 13 (MSB) Data Bit 4 or Data Bit 12 Data Bit 3 or Data Bit 11 Data Bit 2 or Data Bit 10 Data Bit 1 or Data Bit 9 Data Bit 0 (LSB) or Data Bit 8 Address Input 1 Address Input 0 Write Input. Active low. Chip-Select Input. Active low. +12V to +15V Supply-Voltage Input Bias pin for high-temperature, low-leakage configuration 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DGND D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CSMSB LDAC CSLSB WR VDD VSS N.C.
__________Pin Description (MX7535)
PIN NAME REFS REFF RFB IOUT AGNDS FUNCTION Reference Voltage Sense Reference Voltage Force Feedback Resistor. Used to close the loop around an external op amp. Current Output Analog Ground Sense. Reference point for external circuitry. This pin should carry minimum current. Analog Ground Force. Carries current from internal analog ground connections. AGNDS and AGNDF are tied together internally. Digital Ground Data Bit 13 (MSB) Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 (LSB) Chip-Select Most Significant Byte. Active low. Asynchronous Load DAC Input. Active low. Chip-Select Least Significant Byte. Active low. Write Input. Active low. +12V to +15V Supply-Voltage Input Bias pin for high-temperature, low-leakage configuration No Connection. Not internally connected.
MX7534/MX7535
1
2 3 4
1
2 3 4 5
5
AGNDF
6
AGNDF
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DGND D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 WR CS VDD VSS
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5
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
t1 t2 t1 5V 0V t3 t4 5V DATA t5 CS t7 WR t6 0V LDAC 5V 0V WR 5V 0V DATA t t5 6 t5 t6 5V 0V NOTES: 1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90% OF +5V. tR = tF = 20ns. VIH + VIL 2) TIMING MEASUREMENT REFERENCE LEVEL IS t4 t4 CSLSB t3 CSMSB t1 t2 5V 0V 5V 0V 5V 0V t2
A0,A1
NOTES: 1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90% OF +5V. tR = tF = 20ns. VIH + VIL 2) TIMING MEASUREMENT REFERENCE LEVEL IS
2
2
3) IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR, THEN IT MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH.
Figure 1a. MX7534 Timing Diagram
Figure 1b. MX7535 Timing Diagram
_______________Detailed Description
Digital-to-Analog Section
The basic MX7534/MX7535 digital-to-analog converter (DAC) circuit consists of a laser-trimmed, thin-film, 11-bit R-2R resistor array, a 3-bit segmented resistor array, and NMOS current switches, as shown in Figure 2. The three MSBs are decoded to drive switches A-G of the segmented array, and the remaining bits drive switches S0-S10 of the R-2R array. Binary weighted currents are switched to either AGNDF or IOUT, depending on the status of each input bit. The R-2R ladder current is one-eighth of the total reference input current. The remaining seven-eighths of the current flows in the segmented resistors, dividing equally among these seven resistors. The input resistance at REF is constant; therefore, it can be driven by a voltage or current source of positive or negative polarity. The MX7534/MX7535 are optimized for unipolar output operation (analog output from 0V to -V REF), although bipolar operation (analog output from +VREF to -VREF) is possible with some added external components. Figure 3 shows the equivalent circuit for the two DACs. COUT varies from about 90pF to 180pF, depending on the digital code. R0 denotes the DAC'S equivalent output resistance, which varies with the input code.
g(VREF,N) is the Thevenin equivalent voltage generator due to the reference input voltage, VREF, and the transfer function of the R-2R ladder, N.
Digital Section
All digital inputs are both TTL and 5V CMOS logic compatible. The digital inputs are protected from electrostatic discharge (ESD) with typical input currents of less than 1nA. To minimize power-supply currents, keep digital input voltages as close to 0V and 5V logic levels as possible.
__________Applications Information
Unipolar Operation (2-Quadrant Multiplication)
Figures 4a and 4b show the circuit diagram for unipolar binary operation. With an AC input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table 2. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when high-speed op amps are used. Note that the output polarity is the inverse of the reference input.
6
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
REFS* R R R
REFF*
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R/4 G F E D C B A S10 S9 S0 RFB IOUT AGNDS *NOTE: VALID FOR MX7535. IN MX7534, 0REFS AND 0REFF ARE REPLACED BY ONE PIN: REF. AGNDF
Figure 2. Simplified Circuit Diagram
Zero-Offset Adjustment (Figures 4a and 4b)
1) Load the DAC register with all 0s. 2) Adjust the offset of amplifier A1 so that V0 (see figure) is at a minimum (i.e., 30V).
RO
R/4 RFB IOUT + g(VREF, N) - AGNDS ILEAKAGE COUT
Gain Adjustment (Figures 4a and 4b)
1) Load the DAC register with all 1s. 2) Trim potentiometer R1 so that VOUT = -VIN 16383 16384
(
)
Figure 3. Equivalent Analog Output Circuit
AGNDF
In fixed-reference applications, adjust full scale by omitting R1 and R2 and trimming the reference voltage magnitude. In many applications, the excellent Gain Tempco and Gain Error specifications eliminate the need for gain adjustment. However, if trims are required and the DAC is to operate over a wide temperature range, use low-tempco (>300ppm/C) resistors.
Table 1. MX7534 Logic States A1 A2 FUNCTION WR CS
X 1 0 0 0 0 1 X 0 0 0 0 X X 0 0 1 1 X X 0 1 0 1 Device not selected (Note 1) No data transfer DAC loaded directly from Data Bus (Note 2) MS Input Register loaded from Data Bus LS Input Register loaded from Data Bus DAC Register loaded from Input Registers
Bipolar Operation (4-Quadrant Multiplication)
Bipolar or 4-quadrant operation is shown in Figures 5a and 5b. This configuration provides for offset binary coding. Table 4 shows DAC codes and the corresponding analog outputs for Figures 5a and 5b. With the DAC loaded to 10 0000 0000 0000, either adjust R1 for VOUT = 0V, or omit R1 and R2 and adjust the ratio of R5 and R6 for VOUT = 0V. Adjust the amplitude of VIN or vary the value of R7 for full-scale trimming. Resistors R5, R6, and R7 must be matched to 0.003%. Mismatch of R5 and R6 causes both offset and fullscale errors. For wide temperature range operation, use resistors of the same material so that their temperature coefficients match and track.
Note 1: X = Don't Care. Note 2: When A1 = 0 and A0 = 0, all DAC registers are transparent. By placing all 0s or all 1s on the data inputs, the user can load the DAC to zero or full-scale output in one write operation. This simplifies system calibration. 7
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
VIN R1 100 1 REF VDD 19 2 RFB R2 33 3 IOUT C1 33pF VIN LDAC A1 VO CSMSB WR CSLSB 23 22 25 24 D13-DO DGND 8-21 ANALOG GROUND INPUT DATA 7 R1 20 2 1 26 REFF REFS VDD 3 RFB 4 IOUT R2 10 C1 33pF
A0 A1 CS WR
16 15 18 17
MX7534
D7-D0 DGND 7-14 INPUT DATA 6
AGNDS AGNDF VSS 20 5
4
MX7535
AGNDS AGNDF VSS 27 6
5
A1 VO
ANALOG GROUND
Figure 4a. Unipolar Binary Operation
Figure 4b. Unipolar Binary Operation
Grounding Considerations
Since IOUT and the output amplifier noninverting input are sensitive to offset voltages, connect nodes that must be grounded directly to a single-point ground through a separate, very-low-resistance path. Note that the output currents at IOUT and AGNDF vary with input code and create code-dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. To obtain high accuracy, it is important to use a proper grounding technique. The two AGND pins (AGNDF AGNDS) provide flexibility in this respect. In Figures 4a and 4b, AGNDS and AGNDF are shorted together externally and an extra op amp, A2, is not used. Voltage-drops due to bond-wire resistance are not compensated for in this circuit; this could create a linearity error of approximately 0.1LSB due to bond-wire resistance alone. This can be eliminated by using the circuits shown in Figures 6a and 6b, where A2 maintains AGNDS at signal ground potential. By using force/sense techniques, all switch contacts on the DAC are kept at exactly the same potential, and any error caused by bond-wire resistance is eliminated. Figure 7 shows a remote voltage reference driving the MX7535. Op amps A2 and A3 compensate for voltage drops along the reference input line and analog ground line. Figure 8 shows a printed circuit board (PCB) layout with a single output amplifier for the MX7534. The input to REF (Pin 1) is shielded to reduce AC feedthrough, while the digital inputs are shielded to minimize digital
Table 2. Unipolar Binary Code Table
BINARY NUMBER IN DAC REGISTER MSB 11 10 00 00 1111 0000 0000 0000 1111 0000 0000 0000 LSB 1111 0000 0001 0000 ANALOG OUTPUT (VOUT) -VIN 16383 16384 1 -VIN 8192 = - VIN 16384 2 1 -VIN 16384 0V
( ( (
) ) )
feedthrough. The traces connecting IOUT and AGNDS to the inverting and noninverting op amp inputs are kept as short as possible. Gain trim components, R3 and R4, are omitted.
Zero-Offset Adjustment (Figures 6a and 6b)
1) Load DAC register with all 0s. 2) Adjust offset of amplifier A2 for minimum potential at AGNDS. This potential should be 30V with respect to signal ground. 3) Adjust A1's offset so that V OUT is at a minimum (i.e., 30V).
8
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
VIN VIN R1 100 A0 A1 CS WR 16 15 18 17 REF VDD 1 19 2 RFB 3 IOUT R2, 33 C1 33pF R6 20k R7 20k LDAC R5 10k + 4 A1 R8, 5k,10% + A2 VO CSMSB WR CSLSB 23 22 25 24 R1 20 VDD R2 10 C1 33pF 4 IOUT R6 20k R5 10k + 5 A1 R8, 5k,10% A2 + VO R7 20k
1 26 3 2 REFF REFS RFB
MX7534
AGNDS
MX7535
AGNDS
AGNDF D7-D0 DGND VSS 5 7-14 INPUT DATA 6 20
AGNDF D13-D0 DGND VSS 6 7 27 8-21 INPUT DATA
ANALOG GROUND
ANALOG GROUND
Figure 5a. Bipolar Operation
Figure 5b. Bipolar Operation
Gain Adjustment (Figures 6a and 6b)
1) Load DAC register with all 1s. 2) Trim potentiometer R3 so that VOUT = - 16383 VIN 16384
(
)
Table 3. MX7535 Logic States FUNCTION CSMSB CSLSB LDAC WR
0 1 1 0 0 1 0 1 X 1 1 1 0 0 1 1 0 0 0 X 0 X 1 Load MS Input Register Load LS Input Register Load LS and MS Input Registers Load DAC Register from Input Register All registers are transparent. No operation No operation
Low-Leakage Configuration
Leakage current in the DAC flowing into the IOUT line can cause gain, linearity, and offset errors. Leakage is worse at high temperatures. Negatively bias VSS for a high-temperature, low-leakage configuration.
0 1 0 1 X Note:
Dynamic Considerations
In static or DC applications, the output amplifier's AC characteristics are not critical. In higher-speed applications, where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the output op amp's AC parameters must be considered. Another error source in dynamic applications is the parasitic signal coupling from the REF terminal to IOUT. This is normally a function of board layout and lead-tolead package capacitance. Signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough depends on circuitboard layout and on-chip capacitive coupling. Minimize layout-induced feedthrough with guard traces between digital inputs, REF, and DAC outputs.
X = Don't Care.
Table 4. Offset Binary Bipolar Code Table
BINARY NUMBER IN DAC REGISTER MSB 11 10 10 01 00 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 Analog Output (VOUT) +VIN 8191 8192 1 +VIN 8192 0 -VIN -VIN 1 (8192) (8192) = -V 8192
( (
) )
IN
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9
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
VDD R3 100 VDD R4 33 1 19 2 REF VDD RFB IOUT VIN R2 10 2 1 26 3 REFF REFS VDD RFB 4 IOUT RL VO A2 + SIGNAL GROUND VOLTAGE REFERENCE + A1
C1 33pF
R1 20
C1 33pF
3
A1 +
MX7534
D7-D0 DGND VSS 6 20 7-14 INPUT DATA
AGNDS AGNDF 5 4
MX7535
AGNDS 5 A2 +
RL VO
AGNDF D13-D0 DGND VSS 6 7 27 8-21 INPUT DATA
SIGNAL GROUND ANALOG GROUND
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 6a. Unipolar Binary Operation with Forced Ground
Figure 6b. Unipolar Binary Operation with Forced Ground for Remote Load
Table 5. Amplifier Performance Comparisons
OP AMP MAX400 Maxim OP07 AD554L* HA2620* INPUT OFFSET VOLTAGE (VOS) 10V 25V 500V 4mV INPUT BIAS CURRENT (IB) 2nA 2nA 25pA 35nA OFFSET VOLTAGE DRIFT (TC VOS) 0.3V/C 0.6V/C 5V/C 20V/C SETTLING TO 0.003% FS 50s 50s 5s 0.8s
* AD544L is an Analog Devices part; HA2620 is a Harris Semiconductor part.
Compensation
A compensation capacitor, C1, may be needed when the DAC is used with a high-speed output amplifier. The capacitor cancels the pole formed by the DAC's output capacitance and internal feedback resistance. Its value depends on the type of op amp used, but typical values range from 10pF to 33pF. Too small a value causes output ringing, while excess capacitance overdamps the output. Minimize C1's size and improve output settling performance by keeping the PC board trace as short as possible and stray capacitance at IOUT as small as possible.
The MX7534/MX7535 have high-impedance digital inputs. To minimize noise pickup, connect them to either VDD or GND terminals when not in use. Connect active inputs to VDD or GND through high-value resistors (1M) to prevent static charge accumulation if these pins are left floating, as might be the case when a circuit card is left unconnected.
Op-Amp Selection
Input offset voltage (VOS), input bias current (IB), and offset voltage drift (TC VOS) are three key parameters in determining the choice of a suitable amplifier. To maintain specified accuracy with VREF of 10V, VOS should be less than 30V and IB should be less than 2nA. Open-loop gain should be greater than 340,000. Maxim's MAX400 has low V OS (10V max), low I B (2nA), and low TC VOS (0.3V/C max). This op amp can be used without requiring any adjustments. For
Bypassing
Place a 1F bypass capacitor, in parallel with a 0.01F ceramic capacitor, as close to the DAC's VDD and GND pins as possible. Use a 1F tantalum bypass capacitor to optimize high-frequency noise rejection. Place a 4.7F decoupling capacitor at VSS to minimize the DAC output leakage current.
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Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
V+ A2 VDD 2 1 26 3 4 IOUT REFF REFS VDD RFB C1 33pF VPIN 1 AD544*
+
OUTPUT C1 LOCATION RL V0 REF VSS VDD PIN 1 MX7534
MX7535
AGNDS 5
+
A1
AGNDF D13-D0 DGND VSS 6 7 27 8-21 INPUT DATA
A3 + NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
AGND DGND
Figure 7. Driving the MX7535 with a Remote Voltage Reference
medium-frequency applications, the OP27 is recommended. For higher-frequency applications, the HA2620 is recommended. However, these op amps require external offset adjustment (Table 5).
NOTE: LAYOUT IS FOR DOUBLE-SIDED PCB. BOLD LINE INDICATES TRACK ON COMPONENT SIDE.
*AD544 IS AN ANALOG DEVICES PART.
________Microprocessor Interfacing
8086 with MX7535
The MX7534/MX7535 interface to both 8-bit and 16-bit processors. Figure 9a shows the 8086 16-bit processor interfacing to a single MX7535. In this setup, the doublebuffering feature of the DAC is not used. AD0-AD13 of the 16-bit data bus are connected to the DAC data bus (D0-D13). The 14-bit word is written to the DAC in one MOV instruction, and the analog output responds immediately. In this example, the DAC address is D000. Table 6a shows a software routine for Figure 9a. In a multiple DAC system, the double buffering of the DAC chips allows the user to simultaneously update all DACs. In Figure 10, a 14-bit word is loaded to each of the DAC's input registers in sequence. Then, with one instruction to the appropriate address, CS4 (i.e., LDAC) is brought low, updating all the DACs simultaneously.
Figure 8. Suggested Layout for MX7534 Incorporating Output Amplifier
14-bit word is loaded in two bytes, using the MOV instruction. A further MOV loads the DAC register and causes the analog data to appear at the converter output. For the example given here, the appropriate DAC register addresses are D002, D004, and D006. Table 6b shows the program for loading the DAC.
8085A with MX7534
A typical interface circuit is shown in Figure 9c. The DAC is treated as four memory locations addressed by A0 and A1. In standard operation, three of these memory locations are used. Table 6c shows a sample program for loading the DAC with a 14-bit word. The MX7534 has address locations 3000-3003. The six MSBs are written into location 3001, and eight LSBs are written to 3002. Then, with a write instruction to 3003, the full 14-bit word is loaded to the DAC register.
8086 with MX7534
Figure 9b shows an interface circuit to a 16-bit microprocessor. The bottom 8 bits (AD0-AD7) of the 16-bit data bus are connected to the DAC data bus. The
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11
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
MC68000 with MX7535
Figure 11a shows an interface diagram. The following routine writes data to the DAC input registers and then outputs the data via the DAC register: 01000 MOVE.W #W,D0 DAC data, W, loaded into Data Register 0. MOVE.W D0,$E000 Data W transferred between D0 and DAC Register. MOVE.B #228,D7 Control returned to the System. TRAP #14 Monitor Program
ADDRESS BUS 16-BIT LATCH ADDRESS DECODE
ALE
8086
WR AD0-AD15 DATA BUS AD0 *SOME CIRCUITRY OMITTED FOR CLARITY
CSMSB CSLSB LDAC
MX7535*
AD13 WR D0-D13
MC68000 with MX7534
Figure 11b shows the MC68000 interface diagram. The following routine writes data to the DAC input registers and then outputs the data via the DAC register: .A2 E003 Address Register 2 loaded with E003. 01000 MOVE.W #W,D0 DAC data, W, loaded into Data Register 0. MOVEP.W D0,$0000(A2) Data W transferred between D0 and the DAC's Input Register. High-ordered byte transferred first. Memory address specified using the address register indirect plus displacement addressing mode. Address used here (E003) is odd, so data is transferred on the loworder half of the data bus (D0-D7). MOVE.W D0,$E006 This instruction provides appropriate signals to transfer data W from the DAC Input Register to the DAC Register, which controls the R-2R ladder switches. MOVE.B #228,D7 Control returned to the System. TRAP #14 Monitor Program Since this interfacing system uses only the lower half of the data bus, it is also suitable for use with the MC68008, which provides the user with an 8-bit data bus instead of the MC68000's 16-bit bus.
12
Figure 9a. MX7535--8086 Interface Circuit
ADDRESS BUS ADDRESS BUS A2 ALE 16-BIT LATCH ADDRESS DECODE CS A1 A1 A0
MX7534*
8086
WR AD0-AD15 DATA BUS WR D0-D7
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9b. MX7534--8086 Interface Circuit
A8-A15
ADDRESS BUS A1 A0 CS
AE
LATCH
ADDRESS DECODE
8085A
WR AD0-AD7 DATA BUS
MX7534*
WR D0-D7
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9c. MX7534--8085A Interface Circuit
______________________________________________________________________________________
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
Table 6a. Sample Program for Loading the MX7535
00 02 04 07 0B 0E ASSUME DS:DACLOAD,CS:DACLOAD DACLOAD SEGMENT AT 000 8CC9 MOV CX,CS 8ED9 MOVDS,CX BF00D0 MOVDI,#D000 C705"YZWX" MOV MEM,#YZWX EA0000 00FF :DEFINE DATA SEGMENT REGISTER EQUAL :TO CODE SEGMENT REGISTER :LOAD DI WITH D000 :DAC LOADED WITH WXYZ :CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6b. Sample Program for Loading the MX7534 from 8086
ASSUME DS:DACLOAD,CS:DACLOAD DACLOAD SEGMENT AT 000 8CC9 MOV CX,CS MOVDS,CX 8ED9 BF02D0 MOVDI.#D002 MOV MEM,#"MS" C605"MS" 47 INC DI 47 INC DI C605"LS" MOV MEM,#"LS" INC DI 47 47 INC DI MOV MEM,#00 C60500 JMP MEM EA0000
00 02 04 07 0A 0B 0C 0F 10 11 14
:DEFINE DATA SEGMENT REGISTER EQUAL :TO CODE SEGMENT REGISTER :LOAD DI WITH D002 :DAC LOADED WITH "MS"
:LS INPUT REGISTER LOADED WITH "LS"
:CONTENT OF INPUT REGISTERS ARE LOADED TO THE DAC REGISTER :CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6c. Sample Program for Loading the MX7534 from 8085A
2000 01 02 03 04 05 06 07 08 09 0A 0B 0C 200D 26 30 2E 01 3E "MS" 77 2C 3E "LS" 77 2C 77 CF MVIH,#30 MVIL,#01 MVIA,#"MS" MOV M,A INR L MVI A#"LS" MOV M,A INR L MOV M,A RST I
MC6809 with MX7534
Figure 13a shows an interface circuit that enables the MX7534 to be programmed using the MC6809 8-bit microprocessor. Use the 16-bit D accumulator to simplify data transfer. The two key processor instructions are: LDD Load D accumulator from memory STD Store D accumulator to memory
MC6502 with MX7534
Figure 13b shows an interface diagram for the MC6502 using the MX7534.
________________Digital Feedthrough
In the interface diagrams shown in Figures 9-13, the digital inputs of the DAC are directly connected to the microprocessor bus. Even when the device is not selected, activity on the bus can feed through on the DAC output through package capacitance and appear as noise. To minimize noise, isolate the DACs from the digital bus, as shown in Figures 14a and 14b.
Z80 with MX7534/MX7535
Figure 12a is an interface circuit for the Z80, using the MX7535. This is an example of an 8-bit processor interface for these DACs. Figure 12b shows the schematic for the MX7534.
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13
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
ADDRESS BUS A1-A23 ADDRESS BUS
ALE
16-BIT LATCH
ADDRESS DECODE
CS1
8086
WR
CSMSB CSLSB LDAC WR
AS
ADDRESS DECODE
CS4 CS3 CS2
MC68000
DTACK R/W
CSMSB CSLSB LDAC
MX7535*
WR DATA BUS D0-D13 D0-D15
MX7535*
AD0-AD15 DATA BUS D0-D13
CSMSB CSLSB LDAC WR
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 11a. MX7535--MC68000 Interface
MX7535*
D0-D13
A1-A23
ADDRESS BUS A1 A2 A1
AS
MC68000
CSMSB CSLSB LDAC WR DTACK R/W
ADDRESS DECODE
A0 CS
MX7534*
WR D0-D7
MX7535*
D0-D13 *SOME CIRCUITRY OMITTED FOR CLARITY
D0-D7
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 11b. MX7534--MC68000 Interface Figure 10. MX7535--8086 Interface: Multiple DAC Systems
14
______________________________________________________________________________________
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
A0-A15 ADDRESS BUS A0-A15 CSLSB CSMSB LDAC ADDRESS BUS A0 A1 CS
MREQ
ADDRESS DECODE
MREQ
ADDRESS DECODE
Z80
WR
Z80
WR
MX7534*
WR
MX7535*
WR D8-D13 DATA BUS D0-D7
D8-D7
D0-D7
DATA BUS
D0-D7
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 12a. MX7535--Z80 Interface
Figure 12b. MX7534--Z80 Interface
A0-A15 R/W Q E
ADDRESS BUS A0 A1 CS
A0-A15 R/W
ADDRESS ADDRESS BUS BUS A0 A1 CS
ADDRESS DECODE
ADDRESS DECODE
MX7534*
WR
6502
2 D0-D7
MX7534*
WR
MC6809
D0-D7 DATA BUS D0-D7 DATA BUS D0-D7
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 13a. MX7534--MC6809 Interface Circuit
Figure 13b. MX7534--6502 Interface
A0-A15 A0 A1
ADDRESS DECODE EN QUAD LATCH EN QUAD LATCH EN QUAD LATCH A1 CS A0 WR
A0-A15
ADDRESS DECODE
WR MICROPROCESSOR SYSTEM D0-D7
MICROPROCESSOR SYSTEM EN
CSMSB CSLSB LDAC WR
MX7534*
D0-D7
WR D0-D15
16-BIT LATCH
MX7535*
D0-D13
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 14a. MX7534--Interface Circuit Using Latches to Minimize Digital Feedthrough
Figure 14b. MX7535--Interface Circuit Using Latches to Minimize Digital Feedthrough
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15
Microprocessor-Compatible, 14-Bit DACs MX7534/MX7535
___Functional Diagrams (continued)
VDD 26 1 REFS 2 REFF 14-BIT DAC 14 DAC REGISTER 6 MS INPUT REGISTER 8 LS INPUT REGISTER 3 4 5 6 23
_____Pin Configurations (continued)
TOP VIEW
MX7535
RFB IOUT AGNDS AGNDF LDAC REFS 1 REFF 2 RFB 3 IOUT 4 AGNDS 5 CSLSB AGNDF 6 DGND 7 (MSB) D13 8 D12 9 D11 10 D10 11 D9 12 28 N.C. 27 VSS 26 VDD 25 WR
24
MX7535
24 CSLSB 23 LDAC 22 CSMSB 21 D0 (LSB) 20 D1 19 D2 18 D3 17 D4 16 D5 15 D6
22 CSMSB 25 WR 8-21 D13-D0 7 DGND 27 VSS
_Ordering Information (continued)
PART
MX7535KN MX7535JN MX7535KCWI MX7535JCWI MX7535KP MX7535JP MX7535J/D MX7535BQ MX7535AQ MX7535BD MX7535AD MX7535KEWI MX7535JEWI MX7535TQ MX7535SQ MX7535TD MX7535SD
D8 13 D7 14
TEMP. RANGE
0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C
PIN PACKAGE INL (LSBs)
28 Plastic DIP 28 Plastic DIP 28 Wide SO 28 Wide SO 28 PLCC 28 PLCC Dice* 28 CERDIP 28 CERDIP 28 Ceramic SB 28 Ceramic SB 28 Wide SO 28 Wide SO 28 CERDIP 28 CERDIP 28 Ceramic SB 28 Ceramic SB 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2
DIP/SO/PLCC/Ceramic SB
*Dice are tested at +25C, DC parameters only.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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